1. Field of the Invention
The present invention is directed in general to semiconductor devices and methods for manufacturing same. In one aspect, the present invention relates to testing integrated circuits.
2. Description of the Related Art
Integration of optical communication systems into integrated circuit (IC) chip devices is considered a promising solution for overcoming physical limitations in high-frequency, high-density information systems. In addition, a number of optical chip-to-chip interconnect systems have been proposed to provide efficient signal coupling between optical communication systems at different IC chip devices. But with any integrated circuit technology, there are technical difficulties and challenges posed by fabricating such devices, including but not limited to lower yield rates that can result from manufacturing defects that can occur, especially as device geometries shrink, device performance increases, and fabrication technologies advance. These challenges can be compounded when optical communication systems, such as optical micro-electro-mechanical systems (MEMS) circuits and devices, are included in the IC chip devices. While there are various wafer probe tests that may be performed throughout the manufacture of semiconductor devices to detect errors and defects prior to packaging the individual semiconductor die, such tests typically require that each die be separately probed on a tester. In addition, probe testing of integral wafer-contained circuit die for electrical properties has not been successfully extended to testing of electro-optical devices due to a number of challenges posed by generating, delivering, and processing optical test signals, as well as the additional die size requirements imposed by including optical test circuitry in the individual die. As a result, the existing solutions for testing optical communication systems within IC chip devices are extremely difficult at a practical level.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.